Xilinx Vivado Design Suite 2017.2 ISO-TBE

The Vivado® Design Suite offers a new approach for ultra high productivity with next generation C/C++ and IP-based design with the new HLx editions including HL System Edition, HL Design Edition and HL WebPACK™ Edition.

The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.

Accelerating High Level Design
Software-defined IP Generation with Vivado High-Level Synthesis
Block-based IP Integration with Vivado IP Integrator
Model-based DSP Design Integration with System Generator for DSP

Accelerating Verification
Vivado Logic Simulation
Integrated Mixed Language Simulator
Integrated & Standalone Programming and Debug Environments
Accelerate Verification by >100X with C, C++ or SystemC with Vivado HLS

Accelerating Implementation
4X Faster Implementation
20% Better Design Density
Up to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end

Note: SDK is included!

Release Notes 2017.2
Device Support
The following UltraScale+™ devices are in production:
•Kintex
® UltraScale+:
°XCKU13P
•Zynq

® UltraScale+ MPSoC:
°XCZU15EG
New XA Zynq
UltraScale+ MPSoC de
vices introduced:
•XAZU2EG, XAZU3EG
Additional Zynq UltraScale+ MPSoC devices introduced:
•XCZU7EG, XCZU7CG
The following Spartan ® -7 devices are in production and enabled in WebPack:
•XC7S5

Vivado Naming Conventions
The following are the required naming conventions when working with the Vivado Design Suite. Failing to follow these naming conventions might intr
oduce potential risk to the design or the tool, and cause unpredictable behavior in the design flow.

• Source files names must start with a letter (A-Z, a-z) and must contain only alphanumeric characters (A-Z, a-z, 0-9) and underscores (_).
• Output files names must start with a letter (A-Z, a-z) and must contain only alphanumeric characters (A-Z, a-z, 0-9) and underscores (_).
• Project names must start with a letter (A-Z, a-z) and must contain only alphanumeric characters (A-Z, a-z, 0-9) and underscores (_).
•Project directory names must start with a letter (A-Z, a-z) and should contain only alphanumeric characters (A-Z, a-z, 0-9), tilde (~) and underscores (_).

Integrated Simulation (launch_simulation)
• Starting in Vivado 2016.1, the Generate Scripts Only capability has been deprecated and removed from the IDE.
•User should use the Export Simulation capability instead. This provides the functionality for exporting files from Vivado (IP and IP Integrator) to use in external
verification environments.

Vivado Design Suite Documentation Update
In the 2017.2 Vivado Design Suite Documentat ion release, not all documentation will be available at first customer ship. Use the Update Catalog button in DocNav to stay up-to-date with the 2017.2 documentation suite.

Operating Systems
Xilinx® supports the following operating systems on x86 and x86-64 processor architectures.

Microsoft Windows Support
•Windows 7 SP1 Professional (64-bit), English/Japanese.
•Windows 10 Professional Anniversary Edition (64-bit), English/Japanese.

Linux Support
•Red Hat Enterprise Workstation/Server 7.2 and 7.3 (64-bit)
•Red Hat Enterprise Workstation 6.6, 6.7, and 6.8 (64-bit)
•SUSE Linux Enterprise 11.4 and 12.2 (64-bit)
•Cent OS 7.2 and 7.3 (64-bit)
•Cent OS 6.7 and 6.8 (64-bit)
•Ubuntu Linux 16.04.1 LTS (64-bit

iNSTALLATiON NOTES
1) unpack
2) burn / mount
3) install
4) crack dir